Manufacturing of semiconductor devices commonly requires deposition of electrically conductive material on semiconductor wafers. The conductive material such as copper, is often deposited by electroplating onto a seed layer of metal deposited onto the wafer surface by a PVD or CVD method. Electroplating is a method of choice for depositing metal into the vias and trenches of the processed wafer during Damascene and dual Damascene processing.
Damascene processing is a method for forming interconnections on integrated circuits (IC). It is especially suitable for manufacturing integrated circuits, which employ copper as a conductive material. Damascene processing involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). In a typical Damascene process, a pattern of trenches and vias is etched in the dielectric layer of a semiconductor wafer substrate. A thin layer of diffusion-barrier film such as tantalum, tantalum nitride, or a TaN/Ta bilayer is then deposited onto the wafer surface by a PVD method, followed by deposition of seed layer of copper on top of the diffusion-barrier layer. The trenches and vias are then electrofilled with copper, and the surface of the wafer is planarized.
The vias and trenches are electrofilled in an electroplating apparatus, such as the SABRE™ clamshell electroplating apparatus available from Novellus Systems, Inc. of San Jose, Calif., and described in U.S. Pat. No. 6,156,167, which is incorporated herein by reference in its entirety. Electroplating apparatus includes a cathode and an anode immersed into an electrolyte contained in the plating bath. The cathode of this apparatus is the wafer itself, or more specifically, its copper seed layer and the deposited copper layer. The anode may be a disc composed of, e.g., phosphorus-doped copper. The composition of electrolyte may vary, but usually includes sulfuric acid, copper sulfate, chloride ions, and a mixture of organic additives. The electrodes are connected to a power supply, which provides the necessary voltage to electrochemically reduce cupric ions at the cathode resulting in deposition of copper metal on the surface of the wafer seed layer. Ideally, electroplating process should operate at a constant rate across the full wafer surface and should result in uniform thickness of deposited copper layer from the center to the edge of the wafer. Thus, the features near the edge of the wafer should ideally be filled after the same period of process time and under the same current profile as the features near the center of the wafer.
There are several effects, however, that reduce the uniformity of electroplating, leading to increased thickness of deposited copper layer at the edge of the wafer relative to the thickness of copper layer in the center of the wafer. One example is a field effect, which originates from a geometry induced by the shape of electric field in which an increased current flux is present at the edge of the wafer. Unless extensive current shielding is used near the wafer edge, field effect will result in thicker plating in the near-edge area of the wafer.
A terminal effect is also a near-edge effect, the magnitude of which depends on the thickness of the copper seed layer on the wafer. The PVD-deposited copper seed layer can have a thickness typically ranging from about 5 nm to about 150 nm. The sheet resistance of the seed layer increases as its thickness decreases. Using thin seed layers which have a high sheet resistance, a voltage drop exists between the edge of the wafer where electrical contact is made and the center of the wafer. This resistive drop persists during electroplating process until sufficient plating to increase the conductance across the wafer is achieved. The resistive drop results in a larger voltage driving the plating reaction near the edge of the wafer and thus a faster deposition rate at the wafer edge. As a result the deposited layer has a concave profile with an increased thickness near the edge of the wafer relative to its center. The terminal effect substantially increases the plated thickness near the wafer edge in substrates having seed layers or plated layers with a thickness of less then about 1000 Å. The impact of terminal effect in generating thickness variation is mostly concentrated in the outer 15 mm of the wafer diameter, especially in substrates having thin seed layers.
In general, in order to achieve a uniform thickness distribution of plated copper on the wafer surface a uniform voltage profile should exist at the wafer surface during plating. In order to compensate for the terminal effect, it is necessary to compensate for the resistive voltage drop by increasing the voltage or current supplied to the inner regions of the wafer so that an equivalent interfacial potential is maintained across the full wafer surface. Alternatively, one may reduce the sheet resistance by using thick conductive copper seed layers and by choosing symmetry of the anode chamber opening to match the plated wafer surface while adjusting for increased current flux to the edge of the wafer with shielding near the wafer edge. However, thin seed layers are needed for small interconnects which are used in current and future levels of IC miniaturization. Therefore there is a need for methods that will compensate for the terminal effect and lead to uniform deposition of plated metal.
The terminal effect problem has been addressed in a number of ways, which include modifications of electrolyte composition and introduction of new configurations of the plating apparatus.
The plating solution is typically composed of copper sulfate, sulfuric acid, chloride ions and organic additives. Sulfuric acid is added to the electrolyte to enhance conductivity of the plating solution. This allows electrodeposition at reduced applied voltages and improves uniformity of voltage applied to surfaces at varying distances from an anode. Uniform voltages lead to uniform deposition rates. Conversely, when anode and wafer are equidistant at all points, lower concentrations of acid can be used to uniformly increase resistance between the wafer and the anode. This large uniform increase in resistance can diminish the terminal effect of resistive seed layers. Therefore, it is preferred to use electrolytes with low or medium concentrations of sulfuric acid while plating on thin seed layers. For example, an electrolyte having sulfuric acid at a concentration of about 10 g/L corresponding to solution conductivity of about 0.05 (ohm-cm)−1 can adequately redistribute current toward the wafer center during electroplating on moderately resistive seed layers that are thicker than about 400 Å. This method alone, however, does not provide sufficient current redistribution for plating on seed layers thinner than 400 Å.
Copper sulfate is added as a convenient source of cupric ions that undergo reduction to copper metal during electroplating. Very low copper sulfate concentrations significantly increase the polarization resistance at the interface during copper deposition and improve center-edge uniformity by reducing the relative importance of the terminal effect. A degree of center versus edge thickness distribution control can also be achieved by modulating mass transfer rate of cupric ions to the interface such that the deposition process rate becomes limited to some degree in areas of lower mass transfer as described in U.S. Pat. Nos. 6,110,346, 6,074,544, and 6,162,344. This method achieves profile control by using currents which can become a significant fraction of the limiting current and is thus dependent on the copper concentration in the plating bath. Typically, a lower current will be required to achieve some degree of profile control based on copper depletion using a lower concentration of copper in the plating bath.
Organic additives, known as accelerators, suppressors, and levelers, may be added to copper electroplating baths to locally accelerate or suppress electrodeposition of copper and thereby modulate the uniformity of the deposition process. However this method of center-edge distribution control is not normally employed since the additives adsorb on the surface of deposited copper and are incorporated into the electroplated layer thereby altering its properties. In general, however, small amounts of additives may be useful for improving overall uniformity during electroplating because they increase the interfacial polarization resistance and thus diminish the relative magnitude of the terminal effect.
A number of electroplating apparatus configurations have been developed in order to improve the uniformity of electroplating. These configurations include shielding, dynamic shielding, and second cathode configurations. Shielding involves positioning dielectric material between the anode and the wafer cathode. The dielectric inserts, known as shields, can have a variety of geometries allowing them to block the current flow between the anode and the wafer over a portion of the edge of the wafer. These shields, however do not adequately improve nonuniformity resulting from terminal effect, since terminal effect is present only in the beginning of electroplating process. After a sufficient amount of copper is deposited onto the seed layer, its resistance is reduced and the terminal effect disappears. The fixed shields or resistive elements have a constant impact during electroplating process, which can lead to undercompensation of terminal effect during plating on thin seed layers and to overcompensation during deposition on thick seed layers. Therefore, there is a need for configuration, which would allow dynamic modulation of current profile at the wafer surface. Specifically, this configuration should allow for decreased current flux at the wafer edge in the beginning of the plating process, which can be increased as the plating process proceeds.
Such dynamic modulation can be achieved to some degree by employing dynamic shielding which involves movement of an iris like mechanism to divert current toward the center of the wafer as needed to compensate for terminal effect or to achieve specific profile shaping. It has also been described that by inserting a resistive element close to a wafer surface and varying resistivity through the element it is possible to modulate thickness distribution across the wafer. In particular, dielectric plates with hole patterns placed near the wafer surface were described as a means to modulate the resistive pathway between the anode and the wafer. Use of segmented anodes with dynamic control has also been described as a means to divert current towards either the center or the edge of a wafer.
None of these methods, however, accomplishes the goal of achieving a uniform current density across all wafer surfaces during an entire deposition process. Although a final uniform thickness profile can be achieved, it is based on the averaging of conditions throughout a process, rather than a continuous uniform process. Methods which employ dynamic shields and segmented anodes result in sharp transitions in thickness of deposited layer in positions corresponding to anode segment edges or at the edges of the variable shield. These methods are also lacking in ability to specifically modulate thickness at the edge of the wafer where terminal and field effects are most significant.
Introduction of appropriately positioned second cathode known as a thief will divert current from the wafer edge to the second cathode surface, and will allow modulation of thickness of deposited layers. Although several electroplating configurations employing thieving cathodes have been described, the position of the second cathode in these configurations is such that it does not allow sufficient level of control over the current density profile. The second cathode in the previously described configurations is positioned adjacent to the wafer and is immersed with the wafer into the main plating bath during the electroplating process. In such a configuration, the amount of current diverted to the second cathode is governed by the size, the shape and the electric potential of the thief. Modulation of these parameters is not always easily achieved. For example, it is not always possible to position a very large second cathode, which may be needed for diverting large currents, in the immediate proximity of the wafer. Additional difficulties may also exist in changing the thieving cathode geometry to accommodate different process needs or in providing a separate current controller for the thieving cathode.
Positioning the second cathode directly near the wafer also results in increased depletion of metal ion-containing material (e.g. CuSO4) at the wafer surface. Such depletion increases the dependency of the electrodeposition reaction on metal ion mass transfer rate, which is generally undesired.
Furthermore, it is often desirable to strip the metal deposited on the second cathode in order to reuse it after electroplating is completed. Such stripping, which involves reversal of second cathode and anode polarities, cannot be readily achieved with existing second cathode configurations.
Therefore, there is a need for an electroplating apparatus and an electroplating method, which will allow modulation of current density profile during the entire electroplating process.